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Enhancement-Mode MOSFETS As Switches - The NOT Gate


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Enhancement Mode MOSFETS As Switches - THe NOT Gate

Enhancement-mode MOSFETS are primary components in amplification and switching circuits. They are combined in various ways as gates to realize complex switching configurations.

Figure 123.4(a) is an arrangement of a pMOS and an nMOS to form a NOT gate (an Inverter). Figure 123.4(b) is the symbol and Figure 123.4(c) is the truth table for the configuration.
Show how the circuit of figure 123.4(a) functions as an inverter.

The strings: S7P5A51 (Physical Change).

The math:
Pj Problem of Interest is of type change (physical change). Transistors are primarily used for signal amplification and switching. Both are change problems.

Enhancement Mode MOSFETS As Switches - The Not Gate

Figure 123.4(a) is a series connection of a pMOS (blue circle at gate) and an nMOS. In general, pMOS transistors used to build logic gates are called Pull Up Network (PUN) while the nMOS transistors are called Pull Down Network (PDN) because the source of the nMOS is typically connected to ground so that it can pull-down signals in order to realize the binary state 0 (logic 0) while the source of the pMOS is typically connected to a voltage supply so that it can pull-up signals in order to realize the binary state 1 (logic 1).

In figure 123.4(a), source of pMOS is connected to a positive voltage supply while source of nMOS is connected to ground.

For input A = 0, signal = low (logic 0)
pMOS is forward-biased, so it will conduct and current will flow from the pMOS to the output. Output is ON (logic 1).
nMOS is reversed-biased, so it will not conduct and current will not flow to output. Output is OFF (logic 0).

For input A = 1, signal = high (logic 1)
pMOS is reversed-biased, so it will not conduct and current will not flow to output. Output is OFF (logic 0).
nMOS is forward-biased, however, Output remains OFF (logic 0) because source is connected to ground.
So, input = 0 produces output = 1; input = 1 produces output = 0.

A high voltage state at the gate of a pMOS transistor implies the pMOS is OFF and a low voltage state implies the pMOS is ON.
A high voltage state at the gate of an nMOS transistor implies the nMOS is ON and a low voltage state implies the nMOS is OFF.
Consequently, the nMOS and the pMOS are said to complement each other and are therefore called Complementary Metal Oxide Semiconductors (CMOS).

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